This project develops and evaluates deterministic out-of-order parallel simulation for Logical Execution Time (LET) models. The objective is to accelerate simulation-based model validation while preserving the models’ observable timed behaviour. In the models considered, each task job reads its inputs at its logical release and makes its outputs visible at its logical deadline. Our approach exploits these predefined communication relationships to schedule computations according to their data and state dependencies, rather than requiring all tasks to advance through global simulation-time barriers. Computations may finish ahead of their logical output times without changing which values subsequent jobs observe. An initial simulator implementation is available. The requested computing resources will support systematic comparison with a sequential reference simulator and a barrier-based parallel baseline. Experiments will cover synthetic task networks and representative control-oriented models, varying graph structure, task periods, computational workloads, simulation duration, and CPU core count. We will assess simulation correctness, execution time, parallel speedup, synchronization overhead, and memory consumption. Particular attention will be given to identifying both workloads that benefit from parallel execution and workloads whose dependencies limit the available parallelism. Access to multicore CPU resources will enable within-node scaling experiments and repeated benchmark campaigns across a broader range of configurations. The expected outcome is a reproducible experimental assessment of the method’s effectiveness and limitations, supported by benchmark descriptions, experiment scripts, and simulation results. This project is part of doctoral research at Uppsala University. Main supervisor: Wang Yi, Department of Information Technology, Uppsala University, Sweden.