SUPR
Micro-benchmarking SYCL implementations on AMD machines.
Dnr:

NAISS 2024/22-290

Type:

NAISS Small Compute

Principal Investigator:

Hari Abram

Affiliation:

Chalmers tekniska högskola

Start Date:

2024-03-01

End Date:

2025-03-01

Primary Classification:

20206: Computer Systems

Webpage:

Allocation

Abstract

I am micro-benchmarking two main SYCL implementations, AdaptiveCPP and DPCPP, on various architectures. In this microbenchmark study, I am analyzing the overhead of the SYCL constructs and their backend runtime when offloaded to CPUs. This is mainly a characterization study. This micro-benchmarking study will be conducted on two main and ubiquitous CPU architectures x86 and ARM. This study aims to understand the performance differences of various SYCL constructs across different architectures. In this project, I will be characterizing SYCL on AMD machines to understand the performance portability of the SYCL implementations.