This NAISS project is dedicated for the simulations of a computer architecture research: NoCWalk.
NoCWalk is a novel address translation mechanism designed for large scale network-on-chip (NoC) processors. Often times, in a computer architecture that uses multi-level page table, address translations would result in a "page walk", i.e. several memory access in order to translate a virtual address into a physical one. This happens quite often when the computation task has a large data set. Worse, on a NoC-based processor with large number of cores, page walks are more costly because they trigger many communication packets. NoCWalk is a mechanism that turns a centralized page walk consisting of several back-and-forth packet communication into one that does a decentralized round travel, effectively reducing the data traffic incurred by page walks and the "travel distance" of each page walk.